module clok_div_4hz(clk_1khz,clk_4hz,rst);
/*
 *实现1khz -> 4hz 分频
 *实现250分频
 * Author: xianwu Liang
 */
	input clk_1khz;
	input rst;
	output reg clk_4hz;
	reg[6:0] cnt_4hz;
	 
	 //1khz -> 4hz 250分频
	always @(posedge clk_1khz or negedge rst)
		 if(!rst) begin
			  cnt_4hz <= 7'b0000000;
			  clk_4hz <= 1'b0;
		 end
		 else if(cnt_4hz < 7'b1111100) begin
			  cnt_4hz <= cnt_4hz + 1'b1;
		 end
		 else begin
			  cnt_4hz <= 7'b0000000;
			  clk_4hz <= ~clk_4hz;
		 end
		 
endmodule